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: t o  z;|??? 4fdvsf-pdl tm t?????  w- MAX1455 ?? ? ; ? ?????3?? ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 test1 test2 test3 test4 dio unlock v dd2 amp- ampout top view MAX1455 ssop/tssop out inp v ss bdr inm v dd1 amp+ e?  ? ____________________________ 19-2088; rev 1; 10/01 evaluation kit available  j _______________________________ * future product?ontact factory for availability. ** dice are tested at t a = +25?, dc parameters only. ?is????3???????x???3??w7?t k??b{ 4fdvsf-pdlx.byjn*oufhsbufe1spevdut *odw ? apb{ part temp. range pin-package MAX1455eue* -40? to +85? 16 tssop MAX1455aue* -40? to +125? 16 tssop MAX1455eae -40? to +85? 16 ssop MAX1455aae -40? to +125? 16 ssop MAX1455c/d -40? to +85? dice** ???t|7 y [???3??w ? tx?3tw????]b;<^m{xxxnbyjnjddpn ????3??tgl^?h o0xz?t???3tw?s???3????`h?wpb{?t??
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MAX1455 ?? ? ; ? ?????3?? 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +5v, v ss = 0, t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v dd_ to v ss .......................................-0.3v, +6v v dd1 - v dd2 ..............................................................-0.3v, +0.6v all other pins..................................(v ss - 0.3v) to (v dd_ + 0.3v) short-circuit duration, out, bdr, ampout .............continuous continuous power dissipation (t a = +70?) 16-pin ssop (derate 8.00mw/? above +70?) .........640mw operating temperature ranges (t min to t max ) MAX1455eue ..................................................-40? to +85? MAX1455aue ................................................-40? to +125? MAX1455c/d ...................................................-40? to +85? MAX1455eae ..................................................-40? to +85? MAX1455aae ................................................-40? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ................................ +300? parameter symbol conditions min typ max units general characteristics supply voltage v dd 4.5 5.0 5.5 v supply current i dd i dd1 + i dd2 (note 1) 3.0 6.0 ma oscillator frequency f osc 0.85 1 1.15 mhz analog input input impedance r in 1m ? input-referred adjustable offset range offset tc = 0 (note 2), minimum gain 150 mv input-referred offset tempco t a = t min to t max 1 v/ c amplifier gain nonlinearity 0.025 % common-mode rejection ratio cmrr specified for common-mode voltages between v ss and v dd 90 db minimum input-referred fso range (note 3) 7 mv/v maximum input-referred fso range (note 3) 40 mv/v analog output minimum differential signal- gain range pga [3:0] = 0000 39 v/v maximum differential signal- gain range pga [3:0] = 1111 234 v/v low 0.10 clip[1:0] = 00 high 4.90 low 0.15 clip[1:0] = 01 high 4.85 low 0.20 clip[1:0] = 10 high 4.80 low 0.25 output clip voltage settings v out no load, t a = t min to t max clip[1:0] = 11 high 4.75 v load current source v out = +0.5v to +4.5v, t a = t min to t max , clip[1:0] = 00 1ma
MAX1455 ?? ? ; ? ?????3?? _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +5v, v ss = 0, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units load current sink v out = +0.5v to +4.5v, t a = t min to t max , clip[1:0] = 00 2ma dc output impedance 1 ? offset dac output ratio ? v out / ? odac 1.0 v/v offset tc dac output ratio ? v out / ? otcdac 1.0 v/v step response 0% to 63% of final value 300 s output capacitive load 1000 nf output noise dc to 1khz (gain = minimum, source impedance = 5k ? ) 2.5 mv rms bridge drive bridge current i bdr v bdr 3.75v 0.1 0.5 2 ma current mirror ratio 12 m a/m a minimum fsodac code recommended minimum value 4000 hex digital-to-analog converters dac resolution 16 bits odac bit weight ? v ou t / ? c od e , d ac r efer ence = v d d = + 5.0v ( n ote 4) 153 v/bit otcdac bit weight ? v ou t / ? c od e , d ac r efer ence = v bd r = 2.5v ( n ote 4) 76 v/bit fsodac bit weight ? v ou t / ? c od e , d ac r efer ence = v d d = + 5.0v ( n ote 4) 153 v/bit fsotcdac bit weight ? v ou t / ? c od e , d ac r efer ence = v bd r = 2.5v ( n ote 4) 76 v/bit coarse-offset dac irodac resolution excluding sign bit 3 bits irodac bit weight ? v out / ? c od e , input referred, dac reference = v dd = +5.0v (note 4) 9m v /bi t internal resistors current-source reference r isrc 75 k ? ful l - s p an outp ut ( fs o) tr i m resi stor ? r stc 75 k ? resi stor tem p er atur e c oeffi ci ent applies to r isrc and ? r stc 1333 ppm/ c minimum resistance value applies to r isrc and ? r stc 60 k ? maximum resistance value applies to r isrc and ? r stc 90 k ? resistor matching r isrc to ? r stc 1% auxiliary op amp open-loop gain 90 db input common-mode range v cm v ss v dd v output swing no load, t a = t min to t max v ss + 0.01 v dd - 0.01 v
MAX1455 ?? ? ; ? ?????3?? 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +5v, v ss = 0, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units output current drive v out = (v ss + 0.25) to (v dd - 0.25) -1 +1 ma c om m on- m od e rej ecti on rati o cmrr v cm = v ss to v dd 70 db t a = +25 c 1 20 input offset voltage v os v in = 2.5v unity-gain buffer (note 5) t a = t min to t max 25 mv unity-gain bandwidth 2mhz temperature-to-digital converter temperature adc resolution 8 bits offset 3 bits gain 1.45 c/bit nonlinearity 1 lsb lowest digital output 00 hex highest digital output af hex eeprom maximum erase/write cycles (notes 6, 7) 10k cycles erase time (note 8) 7.1 ms a j ?^ ?
q _______________________________________________________________ (v dd_ = +5v, v ss = 0, t a = +25?, unless otherwise noted.) offset dac dnl MAX1455 toc01 dac code dnl (mv) 0 30k 40k 10k 20k 50k 60k 70k -2.5 -1.0 -1.5 -2.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 5.0 2.5 0 -2.5 -5.0 amplifier gain nonlinearity MAX1455 toc02 input voltage [inp - inm] (mv) output error from straight line (mv) -50 -30 -10 10 30 50 odac = +6000hex otcdac = 0 fsodac = 6000hex fsotcdac = 8000hex iro = 2hex pga = 0 output noise MAX1455 toc03 400 s/div out 10mv/div inp - inm shorted together pga = 0hex note 1: excludes sensor or load current. note 2: this is the maximum allowable sensor offset. note 3: this is the sensor? sensitivity normalized to its drive voltage, assuming a desired full-span output of 4v and a bridge voltag e of 2.5v. note 4: bit weight is ratiometric to v dd . note 5: all units production tested at t a = +25 c. limits over temperature are guaranteed by design. note 6: programming of the eeprom at temperatures below +70 c is recommended. note 7: for operation above +70 c, limit erase/write cycle to 100. note 8: all erase commands require 7.1ms minimum time.
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? ___________________________________________________________________ pin name function 1, 15, 16 test1, test3, test2 test pins. connect to v ss or leave unconnected. 2 out analog output. internal voltage nodes can be accessed in digital mode. out can be parallel connected to dio. bypass out to ground with a 0.1f capacitor to reduce output noise. 3 inp positive input. can be swapped to inm by the configuration register. 4 bdr bridge drive output 5 inm negative input. can be swapped to inp by the configuration register. 6v ss negative supply voltage 7v dd1 positive supply voltage 1. connect a 0.1f capacitor from v dd to v ss . 8 amp+ auxiliary op amp positive input 9 ampout auxiliary op amp output 10 amp- auxiliary op amp negative input 11 v dd2 positive supply voltage 2. connect a 0.47f capacitor from v dd2 to v ss . connect v dd2 to v dd1 or for improved noise performance, connect a 1k ? resistor to v dd1 . 12 unlock secure-lock disable. there is a 150a pulldown to v ss . connect to v dd to disable secure-lock and enable serial communication. 13 dio digital input output. single-pin serial communication port. there are no internal pullups on dio. connect pullup resistor from dio to v dd when in digital mode. 14 test4 test pin. do not connect. ?? ? ; ? ?????3?? z?  ? ; a?; z?{7 44 t
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$txz7?s3?????q."9 o ????a???wu?^?om?b{ ??-?3???? %*03????????xz."9q? ????3???g3a?hx?? e??w ? ?83?????? ?t????b{ ."9xz??e??u s8=3?-?? ;
b?mz??e??w????? ? $t u z`?b{ t| w????xz u zd tm?;d pb{???????x t ??????z??????zt|????? pb{??????x7 s-4#7?.4#u
?^? ?b{."9u????t??wz%*0e? w ?????b?h?t m??? ???; pv?b{\?xz ???????qr ^??z ?
$^?h?wpxsme? wt??w!??wy h?pb{??????u????^??  m??$-<>ify
?hx6/-0$,u??t?? ^?om? ?w? ?ud pb{ t
m?-? 3??u?^?om?b{ s8=3?-? ?????z?hx6 s8=?? ! ?t mo ."9t
???7 sw????xz ."9u ??????? 6b?h?t?;^? ?b{ s8=3?-?x?<w?os ifyw??
?pb{ gt p?^????????uz???? ?8=???`?b{??????w ify 7 st -4#
u\?t vz gt p?^???otz fw?u?????pb{."9xz o ? c + w8w 
:q`o???
?;w?-?b? h?tz\w3?-???m?b{fw?zal
\ah c +??????
:xz???
: #*5$-,
q `o o ? $t- ^??b{??w ?o ?yxz s8=3?-?u
?^??
2 ?sxq?nt?  `omsz?ys?sm\qty?`oxi^m{\? t??z103; u?^?z?????? ?hx6/-0$,t?lo%*0?
? b?ud t s??b{ 11111 0 10000000 1 11111 ?? ? ; ? ?????3??
MAX1455 10 ______________________________________________________________________________________ &&130.yt???? page low-byte address (hex) high-byte address (hex) temp-index[7:0] (hex) contents 000 001 00 0 03e 03f 1f 040 041 20 1 07e 07f 3f 080 081 40 2 0be 0bf 5f 0c0 0c1 60 3 0fe 0ff 7f 100 101 80 4 13e 13f 9f 140 141 a0 15e 15f af to ff odac lookup table 160 161 configuration 162 163 reserved 164 165 otcdac 166 167 reserved 168 169 fsotcdac 16a 16b control location 16c 16d 5 17e 17f 180 181 19e 19f 52 general-purpose user bytes 1a0 1a1 80 6 1be 1bf 8f 1c0 1c1 90 7 1fe 1ff af to ff 200 201 00 8 23e 23f 1f 240 241 20 9 27e 27f 3f 280 281 40 a 2be 2bf 5f 2c0 2c1 60 b 2fe 2ff 7f fsodac lookup table ?? ? ; ? ?????3??
6 s8=3?-? ."9x????w6?qz?hx6? 6? ? `?b{6 s8=3?-?xz?<w?ot ''ifyw ??
?pb 3???6 s8=3?-?u ! ?^?h?z ! ? ??x?ct????? y 6t???`z s8=3?-?? 4j?b{?????6?q b?txz6 s8=3?-?w?t s8=3?-? u tsz?ys??d?{ 11111 0 11111111 1 11111 MAX1455 ______________________________________________________________________________________ 11 ? register description config configuration register odac offset dac register otcdac offset temperature coefficient dac register fsodac full-span output dac register fsotcdac full-span output temperature coefficient dac register 5fnq*oefy a j ? temp-index[7:0] temperature (?) decimal hexadecimal -40 20 14 +25 65 41 +85 106 6a +125 134 86 data dio transmit receive high-z high-z transmit host receive transmit high-z receive 11111 1 0 0 0 1 10 1 0 00 0000 000 11 1111111 1111111 11 1 1xx xx weak pullup required weak pullup required
$%* 0 z???????? &&130. 0%"$t|'40%"$????? yt?? temp-index[7:0] eeprom address odac low byte and high byte eeprom address fsodac low byte and high byte 00hex to 7fhex 000hex and 001hex to 0fehex and 0ffhex 200hex and 201hex to 2fehex and 2ffhex 80hex to afhex 100hex and 101hex to 15ehex and 15fhex 1a0hex and 1a1hex to 1fehex and 1ffhex ?? ? ; ? ?????3??
MAX1455 3????????;?????? ."9?wb?ow ???xz??????z ????? ????
zt|????? wt hlom?b{????xz*34w? a??
m?`z?????????
?  ?? *34"
??t|???????? ?
? ??? *34%
????
r`om?b{*34 ????x?<w? pb irs[7:0] = irsd[3:0], irsa[3:0]
?ow??x7 st-4#u
?^??b{?<w qs?z??????t? b?7 sw???x *34"<>pz?????
2w7 4???x*34%<> pb *34w??a?w r x???-?t|a? ??? ?c;t????b{*34 owmw-?3?? ?w??? {?x ??? ????
?i`?b{ \??w-?3??x??t|pzf?g? o ??? $3*-
t 0b????t|6 s8=??pb{ x*34???????? w
?a pb{ o ????w??? $3*--?3?? *34??
?w???w {? t??z {??h????????tb? ??u t??^??b{
?ow&&130.t| ????3??? ?? ?z {v?xz &&130. ??q?tz??x$3*--?3??? ao????b{$3*-xz."9??? z? ?d tb?h?qz z???? 3??????? z?
?%*0 t ?xh?t?????b{ x$3*- ??w
?a pb{ irsa irsd 11111 0 01230123 1 11111 12 ______________________________________________________________________________________ ???a?3??? $0/'*(<>
field name description 15:13 osc[2:0] oscillator frequency setting. factory preset; do not change. 12:11 clip[1:0] sets output clip levels. 10 pga sign logic 1 inverts inm and inp polarity (table 6). 9 iro sign logic 1 for positive input-referred offset (iro). logic 0 for negative iro. 8:6 iro[2:0] input-referred coarse-offset adjustment (table 7). 5:2 pga[3:0] programmable-gain amplifier setting. 1 odac sign logic 1 for positive offset dac output. logic 0 for negative offset dac output. 0 otcdac sign logic 1 for positive offset tc dac output. logic 0 for negative offset tc dac output. 1( "b ?
?  1("<>
pga[3:0] pga gain (v/v) 0000 39 0001 52 0010 65 0011 78 0100 91 0101 104 0110 117 0111 130 1000 143 1001 156 1010 169 1011 182 1100 195 1101 208 1110 221 1111 234 ?? ? ; ? ?????3??
3??????? z? %*0xz???*34 3%*4
?? ify
?$3*--? 3??t {?\qt?loz???? z?q`o ?
r^??b{\w??? ! ?b?qz."9xz *34"<>  ifyw-?3??pz*34??? *41<>
?t?lo> ^?h?a?w??? ??? z?`?b{???x??????q?? ???t??^?h3?????q`o z?^? ?b{ x*341?? ?t&^?h???w apb{  tz3%*3 4??u
???qz."9u%*0 ????? ?pv??otzb?ow%*0?w
? xz ??a??psz?ys??d?{ 3%*3 4?? ? ! ?`h?z."9x???t%*0? ??t? ?`?b{."9x3?????? %*0???t-?`zfw??????? *%0?? t? ?
? z`?b{??????w?t????? t|?????u v?b{?????
? ?z."9??a??%*0x??????? `?b{f?t?."9xz%*0???w?? ?tw??3?-? ! ? j ??qs? ?b{ %*0??? w
???u??a??w ?z ."9w?????
?
2?tuk? \qty?`oxi^m{?`xsm!?
$
? 'wb?h?z\??w z m??? ??%*0???t &;b?\q?
??b{%*0t| ??? z? 065
u
? ^?omsm??-?3?? pxz??? ?x%*0tq
? ^???vpb{ ."9w%*0q??? z?u
? ^?om? ?z ???  z\w? ??????`smpxi ^m{\w yw ??<w3?-???a`o xi^m 
pv?y????loz??? ??%*0 065w???t
? `oxi^m{ 
3%*3 4???
?`oxi^m{ 
a?2
? ???a??`oxi^m ??? e???t
? 
{ 
."9t???? ! ?`?b{ 
a?2
? ?i ?`?b %*006 5??????t ?`?b
{ 
??? ?????`oxi^m{ MAX1455 ______________________________________________________________________________________ 13 iro sign, iro[2:0] input-referred offset correction as % of v dd i n pu t - r ef er r ed o f f set , co r r ec t io n a t v dd = 5vd c in m v 1,111 +1.25 +63 1,110 +1.08 +54 1,101 +0.90 +45 1,100 +0.72 +36 1,011 +0.54 +27 1,010 +0.36 +18 1,001 +0.18 +9 1,000 0 0 0,000 0 0 0,001 -0.18 -9 0,010 -0.36 -18 0,011 -0.54 -27 0,100 -0.72 -36 0,101 -0.90 -45 0,110 -1.08 -54 0,111 -1.25 -63 ?? ??|??? *30<>
?? ? ; ? ?????3??
MAX1455 14 ______________________________________________________________________________________
$tz3%*3 4?? ify
??lo
?^?z ."9uif yw?? ???lo t`om?
! ?3?-?w?u?^?om?b{ o ????
?  s8????z?hx?????t moz ify?? ."9 ow????3?? ?wb?o???b? ?auk??b{ ???t??pxz o ??x ? $t&&130. t?6
\^??\qty?`oxi^m{ ????t??p."9?i ?b?z $-, ???t ?s ??? loxi^m???a ?3???w.4#pb{."9 o ? c + w * t
:uz
\??g t ^?z??? e
t ??? ?3??
??u-?^?z&&130.-?3?? ify &&130. ????a?3????
w ????t- ^??b{ irs command (8 bits) irsa [3:0] irsd [3:0] 0000 dhr [3:0] 0001 dhr [7:4] 0010 dhr [11:8] 0011 dhr [15:12] 0100 reserved 0101 reserved 0110 icra [3:0] ieea [3:0] ieea [7:4] 0111 irsp [3:0] ieea [9:8] 1000 cril [3.0] ( execute ) 1001 atim [3:0] 1010 1011 aloc [3:0] 1100 to 1110 reserved relearn baud rate 1111 icra [3:0] calibration register 0000 config 0001 odac 0010 otcdac 0011 fsodac 0100 fsotcdac 0101 to 1111 reserved cril [3:0] function 0000 load icr 0001 write eeprom 0010 erase eeprom 0011 read icr 0100 read eeprom 0101 0110 0111 1000 to 1111 read irs analog out erase page reserved irsp [3:0] returns 0000 dhr [7:0] 0001 dhr [f:8] 0010 ieea [7:4], icra [3:0] 0011 cril [3:0], irsp [3:0] 0100 aloc [3:0], atim [3.0] 0101 0110 0111 1000 ieea [7:0] ieed [7:0] temp-index [7:0] 1001 1010 to 1111 bitclk [7:0] reserved 11001010 - (use to check communication) bidirectional 16-bit data latch eeprom memory 768 x 8 bits addr data lookup address temp index [7:0] output timer output mux out pga table 9. interface register set commands table 16. internal calibration registers enable analog output dhr [7:0] dhr [15:8] table 10. cril actions table 11. irs pointer functions (reads) dio
$."93?????? t|?????
r
$ ?? ? ; ? ?????3??
????t??p."9?i ?b?z $-, ???t ?s ??? loxi^m???a ?3???w.4#pb{."9 o ? c + w * t
:uz
\??g t ^?z??? e
t ??? ?3??
??u-?^?z&&130.-?3?? ify &&130. ????a?3????
w ????t- ^??b{."9w o ? ???xz ??&?b ?z%"$; zt| ??? ?????; ?
m?`?b{????t??wxz ???a?3???$-,???t&&130. ot??? ? ??
r??
?a? po?\q?
? ?b{$-,???xz??? p?w? ???? e
t? pow4
:? `om?b{ tb;d s ??q e
tu?^?om?b{ ???a?3???t???$-,??? ?wk???!?x."9w????? 63? -? 6 s8=t| s8=??
u?t tsz? ys??d?{??????8izw ?3a wn^?7 gtb?h?txzs p? -4# ?$-, ????!?`oxi^m{ hloz?<t
* ?b? ???a?3???$-,???
?   q? ?`?`h{ 
?   q xz??? ?u7 g ?tx ts?."9??????u|???? b?d
q?wyh?z7 ????? ??lo xi^m{  ?<w?x ?aq^??
ow$-,??t,nm om?b 
&&130.-?3??ify$-,??? t?z$-,??? .4#
? ??pxi^m{ 
???a?3???w$-,???? ???t
? `oxi^m{ 
6 s8=??zt s8= ????? 6
???
?`oxi^m{ 
???a?3???w$-,???? ???t
? `oxi^m{ MAX1455 ______________________________________________________________________________________ 15 *34"?????? irsa[3:0] description 0000 write irsd[3:0] to dhr[3:0] (data hold register) 0001 write irsd[3:0] to dhr[7:4] (data hold register) 0010 write irsd[3:0] to dhr[11:8] (data hold register) 0011 write irsd[3:0] to dhr[15:12] (data hold register) 0100 reserved 0101 reserved 0110 write irsd[3:0] to icra[3:0] or ieea[3:0] (internal calibration register address or internal eeprom address nibble 0) 0111 write irsd[3:0] to ieea[7:4] (internal eeprom address, nibble 1) 1000 write irsd[3:0] to irsp[3:0] or ieea[9:8] (interface register set pointer where irsp[1:0] is ieea[9:8]) 1001 write irsd[3:0] to cril[3:0] (command register to internal logic) 1010 write irsd[3:0] to atim[3:0] (analog timeout value on read) 1011 write irsd[3:0] to aloc[3:0] (analog location) 1100 to 1110 reserved 1111 write irsd[3:0] = 1111bin to relearn the baud rate 
m?-?3?? $-<>
field name description 15:8 cl[15:8] reserved 7:0 cl[7:0] control location. secure-lock is activated by setting this to ffhex, which disables dio serial communications and connects out to pga output. ?? ? ; ? ?????3??
MAX1455 
6 s8=??zt s8= ????? 6
???
?`oxi^m{ o ? c +w * t
:xz#*5$-,<>w ?? ??\qt ?lo t? ypv?b{\w???w
:xz ? ????w??? ?????
t 0 b?z o ? c +???
:? `om?b{ &&130.?w ??q {? o ?&&130.xz1lb??a????b? t
?ilo ''ify t
? ^?h???
??^?s z?ys??d?{."9txz?? ifyq ??#if y? ?vz? ?w ?? y 6p??^??b{ ??ifyw .4#tx o ? c +???? 3??
? u??om?b{??#ifyxz 6/-0$, ytsx3??? ?ud s?ot ifyt
? ^?om?b{ &&130.? ??b? ?z?c?? ifyw .4# ?- `oxi^m{ ???z\??w???xz  ifyw?????? ?q?tz6 s {?? sz?ys??d?{ \??w ??6 {?b?
2t ??w ?o? ?tsmpxi^m{ o ?&&130.xz&3"4&????lo
?t ?? b?tz?hx1bhf&sbtf?? 
??lo ? $ ??upv?b{1bhf&sbtf??? c? `h?z n t 4m ?auk??b{ n tu&ab?
2tz ? ?qw ?z?hx ?ow ?????qz &&130. ot ??  y 6u c
\b?\quk??b{ &&130. 1bhf&sbtf??
ow??? ??b? tx7 stz*34-?3??*&&"<>? ?as ?? j? 
???`oxi^m{f?t?z $3*- 1bhf&sbtf?? ify
?
?`oxi^m{ &&130.???? {?tx???? "eesftt <>
??loz *34 -?3??*&&"<>z *&&"<>zt|*&&"<>???`oxi^m{ {??????? %bub<>
??lo*34-? 3??%)3<>t|%)3<>???`oxi^m{ &&130. 83*5& ???$3*- ify
t
?`o xi^m{ &&130.t???? ?? ?tx 
???? "eesftt<>
??loz*34-? 3??*&&"<>z*&&"<>zt|*&&"<>? ??`oxi^m{ 
3&"% &&130.???$3*-? ify
t
?`oxi^mz\?u ?as&&130.??? %)3<>???`?b{ 
ify %)3<>?&?
??lo*34-?3?? *341<>???`oxi^m{ 
3&"% *341???$3*-? ify
t
?`oxi^m{ ???=??? z? ."9xz?????? 3e"mh
????m ????t??tsmoz??? ??? z?b? ; ? ?`om?b{ 3e"m h?? ! ???? ??pz"-0$<>? 
t?lo>  ^?? o ???? ??uz."9065??? ?=^??b{\w ??xz"5*.<>? u
? b?8 065t
? ^?om?b{"5*.; 16 ______________________________________________________________________________________ $3* -???? cril[3:0] name description 0000 ldicr load internal calibration register at address given in icra with data from dhr[15:0]. 0001 eepw eeprom write of 8 data bits from dhr[7:0] to address location pointed by ieea [9:0]. 0010 erase erase all of eeprom (all bytes equal ffhex). 0011 rdicr read internal calibration register as pointed to by icra and load data into dhr[15:0]. 0100 rdeep read internal eeprom location and load data into dhr[7:0] pointed by ieea [9:0]. 0101 rdirs read interface register set pointer irsp[3:0]. see table 11. 0110 rdalg output the multiplexed analog signal onto out. the analog location is specified in aloc[3:0] (table 13) and the duration (in byte times) that the signal is asserted onto the pin is specified in atim[3:0] (table 14). 0111 pageerase erases the page of the eeprom as pointed by ieea[9:6]. there are 64 bytes per page and thus 12 pages in the eeprom. 1000 to 1111 reserved reserved. ?? ? ; ? ?????3??
x ???????????w??q`o?m ?b{ ?ix ?? `oxi^m{"5*.<> ?t??>??8w7?tz??? ??u ??? z?t?
~ ?^?z065u??a?? y 6t??b{."9xz065w??a?? y 6ulot???pz%*0 w??? ! ? pv?b{\wmow?????u
$t?^?om ?b{ ."9%*0xz??? z?u??a?s?? a?? y 6pb{\?x065t|%*0??t
?  b?\q?d tb?h?pb{%*0t|065u?t
? ^?om? ?z??e???."9 ?w??-?3??
? u??a??psz? ys??d?{\w ?a eu%*0?wb?ow
? u ?t??a??pk?8? c
\`z\w8 %*0? m??? ?w &;u ?aqs??b{ ??? z?wh?t  z?t??uk??b{\? x"5*.<>? 'ify t
? b?\qt?lo
? r^? ?b{\wt??xz%*0t|065u m`om? ? w??;pv?b{\wt??p3%"mh??z?h x w??? ! ?`h?z%*0x ?? ??w8??a?? y 6pb{ t\w8u &ab?q%*0x ! ?t??t ??zw?? ?? ? !z?b{ t??px??? z?x t?? a?pb{ ? 065t
? ^?om?z o ???? ??x? ??^??d?{\??w o ? ??wmu ^?o m?t065??????b?q ?)u c
\b? \quk??b{ #%3z'405 $srw o ? ??? ?? lom?065???`smpxi^m{ ??-?3????w? ?<t."9 ow7?s; ;w??3? -?w??
??p?[?`h ?  ????
? ?!?`z ??? y`oxi ^m{6 s8=???
?b?
2t3aw ????u!?^?hh?t."9qw ? u???h ?z s8= e?- ab?h??? ???? &;`oxi^m{ MAX1455 ?? ? ; ? ?????3?? ______________________________________________________________________________________ 17 *34 1??? irsp[3:0] returned value 0000 dhr[7:0] 0001 dhr[15:8] 0010 ieea[7:4], icra[3:0] concatenated 0011 cril[3:0], irsp[3:0] concatenated 0100 aloc[3:0], atim[3:0] concatenated 0101 ieea[7:0] eeprom address byte 0110 ieed[7:0] eeprom data byte 0111 temp-index[7:0] 1000 bitclock[7:0] 1001 reserved. internal flash test data. 1010-1111 11001010 (cahex). this can be used to test communication. $- ,?? ???a?3?? ?w.4#
clk code (bin) clock adjustment (%) 011 +27 010 +18 001 +9 000 0 111 -9 110 -18 101 -27 command action ffhex reinitialize part ready for baud rate learning. change system baud rate to new value. 01hex learn baud rate. f8hex load 15 (fhex) to irsp[3:0] register. 59hex read irs. host computer must be ready to receive data on the serial line within 1 (baud rate) byte time of sending the read irs command. the MAX1455 returns cahex. (irsp values of 10 to 15 are configured to return cahex for communication checking purposes.)
MAX1455 18 ______________________________________________________________________________________ ? ????? ???? ??pxi^m{ 5fnq*oefy command action 78hex load 7 to irsp[3:0] register. 59hex read irs. host ready to receive data within 1 byte time of sending the read irs command. the MAX1455 returns the current temp-index pointer value. ? ????p 065e? #%3  ????`?b{ command action 1bhex load 1 (bdr measurement) to aloc[3:0] register. cahex load 12 to the atim[3:0] register: (2 12 +1) ? 8/9600 = 3.4s. 69hex rdalg. the dio pin is three-stated and the out pin is connected internally to the bdr pin for a duration of approximately 3.4s. ? $???3??'40%"$?t {?pxi^m{ command action 00hex load 0 hex to the dhr[3:0] register. 41hex load 4 hex to the dhr[7:4] register. c2hex load c hex to the dhr[11:8] register. 83hex load 8 hex to the dhr[15:12] register. 36hex load 3 (fsodac) to the icra[3:0] register. 09hex ld icr. 8c40 hex is written to the fsodac register. ? 5fnq*oefyp$ify? '40%"$??? ?? -?3??t {?pxi^m{\w?xz &&130.wb??3??????b?wtz fw?3??t ob?mc?w????-?^?? ?ausm\q?
y `oz1bhf&sbtf??? ?m?b{ command action a6hex load ahex (page number corresponding to eeprom locations 280hex and 281hex) to the ieea[3:0] register. 79hex page erase command. wait 7.1ms before sending any further commands. 06hex load 0hex to the ieea[3:0] register. 87hex load 8hex to the ieea[7:4] register. 28hex load 2hex to the ieea[9:8] (irsp[3:0]) register. 00hex load 0hex to the dhr[3:0] register. 41hex load 4hex to the dhr[7:4] register. 19hex write eeprom. 40hex is loaded to eeprom address 280hex, which is the low byte location corresponding to a temp-index pointer value of 40. 16hex load 1 to the ieea[3:0] register. ieea[7:4] and ieea[9:8] already contain 8 and 2, respectively. c0hex load chex to the dhr[3:0] register. 81hex load 8hex to the dhr[7:4] register. 19hex write eeprom. 8chex is loaded to eeprom address 281hex, which is the high byte location corresponding to a temp- index pointer value of 40. ?? ? ; ? ?????3??
MAX1455 ______________________________________________________________________________________ 19 "-0$ [ aloc[3:0] analog signal description 0000 out pga output 0001 bdr bridge drive 0010 isrc bridge drive current setting 0011 vdd internal positive supply 0100 vss internal ground 0101 clip-top clip voltage high value 0110 clip-bottom clip voltage low value 0111 fsodac full-scale output dac 1000 fsotcdac full-scale output tc dac 1001 odac offset dac 1010 otcdac offset tc dac 1011 vref bandgap reference voltage (nominally 1.25v) 1100 vptatp internal test node 1101 vptatm internal test node 1110 inp sensor s positive input 1111 inm sensor s negative input weak pullup required 11111 0 1001 0 1 0 1 1111111 x1111111 xx xxxx xxx 1x x 1 0 2 atim + 1 byte times data out valid output high-z 1 xx xx weak pullup required high-z receive receive high-z dio transmit high-z transmit host
$??? z?????? ?? ? ; ? ?????3??
MAX1455 ?4 ?w?a 4 ?x ?^y?t|9 s c?t?h??
q wu a ? ?aq`?b{ ?sxq?mw?gy? ?z? t|???
t|mw9 s??loxi^m{?g y?t|9 s?
??b\qt??z^?t
^ sw?m alu ????b{ a js4 ?  qx?<w?ot ?q????b 20 ______________________________________________________________________________________ "5*. [ atim[3:0] duration of analog signal specified in byte times (8-bit time) 0000 2 0 + 1 = 2 byte times, i.e., (2 ? 8) / baud rate 0001 2 1 + 1 = 3 byte times 0010 2 2 + 1 = 5 byte times 0011 2 3 + 1 = 9 byte times 0100 2 4 + 1 = 17 byte times 0101 2 5 + 1 = 33 byte times 0110 2 6 + 1 = 65 byte times 0111 2 7 + 1 = 129 byte times 1000 2 8 + 1 = 257 byte times 1001 2 9 + 1 = 513 byte times 1010 2 10 + 1 = 1025 byte times 1011 2 11 + 1 = 2049 byte times 1100 2 12 + 1 = 4097 byte times 1101 2 13 + 1 = 8193 byte times 1110 2 14 + 1 = 16,385 byte times 1111 in this mode, out is continuous; however, dio accepts commands after 32,769 byte times. do not parallel connect dio to out. *$3"??? icra[3:0] name description 0000 config configuration register 0001 odac offset dac register 0010 otcdac offset temperature coefficient dac register 0011 fsodac full-scale output dac register 0100 fs o tc d ac full-scale output temperature coefficient dac register 0101 reserved. do not write to this location (eeprom test). 0110 to 1111 reserved. do not write to this location. ?? ? ; ? ?????3??
????9 s?
?  ?z?
 ."9?a ?yt?-b?h?z???? 
:? ?qyz|???z'40t|?? ? w  ?t,nmh
?lof?g?w?? ??b?\qt?lo?????? s8= `oxi^m{ o ?????3???xz *$3"<>t??^?z t?^???ot ???^??b{ s8?? ?y '40%"$p
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$ ??g3aw? ?  4 ??l typical uncompensated input (sensor) typical compensated transducer output offset .. . . 100% fso fso . ....1mv/v to 40mv/v offset tc ...20% fso offset tc nonlinearity .. .4% fso fsotc .. ..-20% fso fsotc nonlinearity .. .. .5% fso temperature range.. . . ..-40 c to +125 c out.. . rati om etr i c to v dd at 5.0v offset at +25 c 0.500v 200v fso at +25 c ...4.000v 200v offset accuracy over temp. range . .. 4mv ( 0.1% fso) fso accuracy over temp. range .. 4mv ( 0.1% fso) ?? ? ; ? ?????3??
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? upv?b{ ?? ?c __________________________ transistor count: 62,242 process: cmos substrate connected to: v ss 22 ______________________________________________________________________________________ 80 60 0 20 40 040 20 60 80 100 raw sensor output (t a = +25 c) pressure (kps) v out (mv) 0 1 3 2 4 5 040 20 60 80 100 compensated transducer (t a = +25 c) pressure (kps) v out (v) -20 10 30 20 -10 0 uncompensated sensor temperature error temperature ( c) error (% fso) -50 50 0 100 150 fso offset -0.15 -0.05 -0.10 0.05 0 0.10 0.15 -50 50 0 100 150 compensated transducer error temperature ( c) error (% fso) fso offset
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MAX1455 ?? ? ; ? ?????3?? ______________________________________________________________________________________ 23 v dd v dd v ss v ss ? eeprom (lookup plus configuration data) v dd v ss v dd v ss fso dac unlock v dd1 16 bit 16 bit 8-bit lookup address bandgap temp sensor pga mux mux fsotc register r stc 75k ? r isrc 75k ? bdr inp inm fsotc dac v ss eeprom address 15eh + 15fh 000h + 001h : offset dac lookup table (176 ? 16 bits) configuration register shadow usage 19eh + 19fh 16ch + 16dh : user storage (52 bytes) 2feh + 2ffh 1a0h + 1a1h : fso dac lookup table (176 ? 16 bits) 160h + 161h reserved 162h + 163h offset tc register shadow 164h + 165h reserved 166h + 167h fsotc register shadow 168h + 169h control location register 16ah + 16bh offset dac 1 1 ? 24 phase reversal mux out amp- ampout amp+ pga gain 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 9.0 8.5 pga (3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1111 1110 total gain 39 52 65 78 91 104 117 130 143 156 169 182 195 208 234 221 iro (3, 2:0) offset (mv) 63 54 45 36 27 18 9 0 0 -9 -18 -27 -36 -45 -63 -54 1,111 1,110 1,101 1,100 1,011 1,010 1,001 1,000 0,000 0,001 0,010 0,011 0,100 0,101 0,111 0,110 v ss 16 bit offset tc dac otc register input-referred offset (coarse offset) programmable gain stage uncommitted op amp value v ss to v dd 20mv v ss , v dd 0.01v v ss , v dd 0.25v 10mhz typical parameter i/p range i/p offset o/p range no load 1ma load unity gbw pga bandwidth 3khz 10% 16 bit *input-referred offset value is proportional to v dd . values given are for v dd = +5v. v ss pga bandwidth 3khz 10% v ss v dd2 dio digital interface test 1 test 2 test 3 test 4 clip-high dac clip-low dac ????3??????? ___________________________________________________
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